1. Field of the Invention
The invention relates to an asynchronous transfer mode (ATM) network switch. More particularly, the invention relates to an ATM switch having cell buffers for each virtual connection (VC) and means for outputting cells according to their VC priority.
2. State of the Art
In ATM data transmission cells of data conventionally comprising fifty-three bytes (forty-eight bytes carrying data and the remaining five bytes defining the cell header, the address and related information) pass through the network on a virtual connection at an agreed upon ate related to the available bandwidth and the level or service paid for. The agreed upon rate will relate not only to he steady average flow of data, but will also limit the peak flow rates.
Over an extensive network, cells on a virtual connection can become bunched together with different cells having different delays imposed upon them at different stages, so that the cell flow on a VC then does not conform with the agreed upon rates. To prevent rates being exceeded to the detriment of other VCs in the network, the network will include, for example at the boundary between different networks, means for policing the flow. The flow policing means typically includes a xe2x80x9cleaky bucketxe2x80x9d device which asses the pea and average flow rates of cells on a VC and if required either downgrades the cell""s priority or discards cells. An example of such a device is disclosed in co-owned UK Patent Application No. 9505358.3 which is hereby incorporated herein in its entirety.
Since policing can result in the discarding of cells which should not be discarded, it is desirable to effect xe2x80x9ctraffic shapingxe2x80x9d to space out the cells on a VC sufficiently so as to ensure that they meet the agreed upon rates, and in particular the peak rates. A problem with traffic shaping is that it is desirable to delay the transmission of cells by variable amounts in an attempt to avoid cell loss. In practice, however, variable cell delay has been difficult to implement. Co-owned UK Patent Application No. 9509483.5, which is hereby incorporated herein in its entirety, discloses an ATM switch with a traffic shaping mechanism which delays the transmission of incoming cells by varying amounts of time and which accounts for both peak and average cell flow rates. The traffic shaping mechanism broadly comprises means for determining for each cell received an onward transmission time dependent upon the time interval between the arrival of the cell and the time of arrival of the preceding cell on the same VC, buffer means for storing each new cell at an address corresponding to the onward transmission time, and means for outputting cells from the buffer means at a time corresponding to the address thereof. The traffic shaping mechanism results in cells being output at a rate which is related to the rate at which they are received which eliminates or minimizes bunching.
In some instances, however, it is desirable to provide a more even output of cells, regardless of the rate at which they are received. For example, different virtual connections may have different priority levels. Presently, the ATM standard provides for four different priority levels. In order to assure that a priority level is maintained, it may be necessary that cells having a high priority level be output before cells having a low priority level, regardless of the rate at which the cells are received.
It is therefore an object of the invention to provide an ATM switch with means for controlling the flow of cells through the switch according to VC priority.
It is also an object of the invention to provide an ATM switch with means for controlling the flow of cells through the switch according to VC priority and with means for preventing blockage of low priority cells.
It is an other object of the invention to provide an ATM switch with means for controlling the flow of cells through the switch according to VC priority and which also allows traffic shaping.
In accord with these objects which will be discussed in detail below, an ATM switch according to the invention includes a plurality of slot controllers each having at least one external network link and a link to a switch fabric, the slot controllers receiving ATM cells from the network and transmitting cells to other slot controllers via the switch fabric and receiving cells from the switch fabric and transmitting cells onto the network. Each slot controller is provided with a plurality of FIFO buffers, one cell FIFO for each VC established on the switch and one arbitration FIFO for each priority level, and a FIFO controller. According to the methods of the invention, when a cell enters a slot controller the cell header is examined to determine the VCI and the priority level. The slot controller examines the switch fabric to find a path for the VC, selects a VC FIFO for the VC, pushes the cell into the VC FIFO, increments a counter for the VC FIFO, an, if the VC FIFO was previously empty, writes a pointer to the arbitration FIFO for the priority level of the cell FIFO. The arbitration FIFOs are examined according to a schedule and cells are popped from VC FIFOs according to priority for exit from the slot controller. According to one embodiment of the invention, the highest priority arbitration FIFO is always examined first and none of the lower priority arbitration FIFOs are examined unless the highest priority arbitration FIFO is empty. According to another embodiment of the invention, timers are set for the lower priority arbitration FIFOs and if a timer expires for a lower priority arbitration FIFO, it is examined regardless of the contents of the highest priority arbitration FIFO. According to still another embodiment of the invention, the slot controllers are coupled to two switch fabrics and two sets of arbitration FIFOs are used, one set for each switch fabric. Prior to popping a cell from a FIFO into the switch fabric, the switch fabric is examined to determine if the path is broken and whether an alternate path exists through the second switch fabric. If an alternate path is available, the cell is not sent, but the pointer for the VC FIFO is pushed into the corresponding arbitration FIFO for the second switch fabric.
According to the invention, the FIFO buffers may be arranged only to buffer the flow of cells from the slot controller into the switch matrix. Alternatively, a second set of FIFO buffers may be arranged to buffer the flow of cells from the switch matrix into the slot controller. The buffering system of the invention may be used with or without traffic shaping
Additional objects and a vantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures.